1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. More particularly, the present invention relates to a power MOSFET array structure located under a gate pad.
2. Description of Related Art
Power MOSFET can be used as high voltage device with current applicable operating voltage of up to higher than 4500 volts, and is mainly used as switching apparatus. Commonly, the MOSFET is of a planar structure, and each end point in the transistor is only several micrometers away from a chip surface. All the power devices are of a vertical structure, such that the devices can bear high voltage and high current at the same time. The bearable voltage of the power MOSFET depends on doping concentration and thickness of n-type epitaxy layer, and the current capable of passing through the power MOSFET depends on channel width of the device. The wider the channel is, the more current can be accommodated. Under fixed channel size, the current is directly proportional to channel density. Generally speaking, in the conventional art, the channel density is increased by means of reducing distance between basic devices. When volume of the transistor is reduced, not only the space is saved, but also the cost is reduced. Therefore, the industry urgently needs a method of reducing the volume of the power MOSFET array.
The basic devices of the MOSFET array include a substrate, an epitaxy layer, a source region, gates, a source pad, and a gate pad etc. In the conventional art, the source pad is disposed above the power MOSFET array and is connected to the source region, and the gate pad is disposed beside the array and is connected to the gate. A space exists under the gate pad, and is useless. Therefore, the industry urgently needs a method of well utilizing the space under the gate pad, thereby reducing the volume of the array and increasing the device integration.